A ROM, which is a read only memory device, is widely used in a variety of electric, electronic products.
Recently, with the progress of digital signal processing techniques, a demand of ROM has been increased and the development of semiconductor manufacturing techniques has enabled a circuit system for performing a specific function to be constructed by one chip.
For example, a Digital Audio Tape recorded (DAT), which can produce an excellent tone quality by processing an audio signal digital, comprises an only digital signal processor chip, namely, a DSP chip.
A DSP chip, which is a CMOS logic VLSI having a very large integration degree, includes several ROM, RAM and peripheral logic circuits within one chip. An existing ROM circuit built in a DSP chip by a static CMOS design has a problem that the size of a whole DSP chip comes to large due to the enlargement of the required area.
FIG. 1 is a circuit diagram of a 2.times.3 static ROM by a prior CMOS design method. In FIG. 1, a ROM circuit is largely devided into a decoder 1 and an encoder 2.
A decoder 1 generates the 4-bit word signal by decoding the 2-bit address signal A.sub.0, A.sub.1 inputted. A decoder 1 contains the four AND gates G.sub.1 to G.sub.4 and its output terminals are connected to the word lines W.sub.0 to W.sub.3 which, are driven according to the input states, respectively.
An encoder 2 consists of an AND circuit portion 3 made up a first conductive type, for example, P-channel MOS transistors and an OR circuit portion 4 made up a second conductive type, for example, N-channel MOS transistors.
An AND circuit portion 3 and an OR circuit portion 4 are connected to three output lines D.sub.0 to D.sub.2. At the cross section of the word lines W.sub.0 to W.sub.3 and the output lines D.sub.0 to D.sub.2, respectively, the OR circuit portion 4 is a region in which the desired data are memorized by being programmed according to the combinational existence of the N-channel MOS transistors in performing a manufacturing process.
A drain electorde of each of the N-channel MOS transistors is connected to an output line, a gate electrode is connected to the word line and a source electrode is connected to a first voltage supply power source (Vss or grounded voltage).
In the AND circuit portion 3, the P-channel MOS transistors (having the same number as the bit number of an address signal) are serially connected between each output line and a second voltage supply power source (VDD). The gate electrodes of the P-channel MOS transistors are respectively connected to word lines (for example, the word lines W.sub.1, W.sub.2). The output lines D.sub.0 to D.sub.2 are driven by these P-channel MOS transistors.
The output states corresponding to the address signals of the ROM circuit as described above are shown in the following Table 1.
TABLE 1 ______________________________________ A.sub.1 A.sub.0 W.sub.0 W.sub.1 W.sub.2 W.sub.3 D.sub.1 D.sub.2 D.sub.3 ______________________________________ 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1 1 0 1 ______________________________________
Therefore, the ROM circuit of the prior CMOS design method as described above should simultaneously possess the P-channel MOS transistors corresponding to the N-channel MOS transistors.
Moreover, because a mobility of carriers in the P-channel MOS transistor is slow compared with the N-channel MOS transistor, the P-channel MOS transistor occupied a still more large area due to the relatively wide channel width.
Also, because a wiring region is required in order to connect the word lines corresponding to the AND circuit portion 3 comprising P-channel MOS transistors, the area of a wiring region comes to be large in porportion as a memory capacitance becomes large.